The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS) while others can use either the Silicon-Germanium (SiGe) or Gallium Arsenide (GaAs) technology to form the dice in these designs. At 60 GHz, achieving the desired parameters of frequency synthesis using VCOs and high performance dividers present difficult challenges.
Oscillator and frequency synthesizers are elements in communication systems. The highest performance circuits in a given technology are usually measured in some form of an on-chip oscillator, such as a ring oscillator using transistors or a resonate oscillator that uses transistors and reactive components in a regenerative connection.
The frequency synthesizers are typically phase locked loops (PLL). A PLL generates a high frequency clock signal using a voltage controlled oscillator (VCO) and compares this signal against a reference frequency. A stable low frequency signal based, for example, on a crystal is used as one of the reference frequencies within the phase lock loop. The negative feedback within the phase lock loop suppresses any phase noise due to the oscillator that generates the high frequency clock signal and allows the generation of stable high frequency clock signals. A VCO is designed in a given technology to achieve the maximum possible performance and push against the edge of technology boundaries to generate a high frequency clock signal. This clock signal has such a short duration (16 ps) at 60 GHz that any conventional computational CMOS gate being clocked by this signal would fail since the duration is so short. A prescalar is a circuit that divides down the high frequency clock signal to provide more time to calculate a computation. The conundrum is that the prescalar is itself a computational unit.
The prescalar produces a lower frequency clock signal which provides more time to demanding circuits so that they can perform their required functions. However, a conventional CMOS divide-by-2 is not capable of operating at a clock rate of 60 GHz. An injection locked divider is typically used to create a high frequency divider. But the injection locked divider has limitations; 1) injection locked dividers have a very narrow locking range; and 2) commercial production of injection locked divider has not been well proven. Apparatus and methods are presented to overcome these limitations. A divide-by-2 is presented that incorporates these advances thereby eliminating the need for the injection locked divider.